1. Field of the Invention
Embodiments of the invention relate to electronic devices, and more particularly, to electronic devices including a delay-locked loop (DLL).
2. Description of the Related Art
High speed electronic devices such as DRAM are often provided with external or reference clock signals for timing the operations of their internal components. When an external clock signal is propagated to internal components, a time delay of the clock signal occurs. The internal components may not be well synchronized with the external clock signal, which can affect the performance of the internal components at relatively high speeds.
In addition, various components in an electronic device can have different manufacturing parameters. Thus, the components in an electronic device may not be relatively well synchronized even though they are clocked by the same external or reference clock signal. In addition, variations in operating conditions such as operating temperature and external power supply may also vary propagation delay, resulting in changes to clock delay.
FIG. 1 illustrates a conventional delay-locked loop (DLL) system 100. The DLL system 100 includes an input buffer 105, a delay line 115, a clock tree 117, an output buffer 120, a replica model 125, a phase detector 140, a shift register controller 142, a shift register 145, and internal circuits 170. The input buffer 105 receives an external clock signal CLK and the output buffer 120 outputs an output clock signal CLK_DLL.
The delay line 115, the replica model 125, the phase detector 140, the shift register controller 142, and the shift register 145 together form a delay-locked loop (DLL). The DLL is configured to synchronize the external clock signal CLK with the output clock signal CLK_DLL.
The input buffer 105, the delay line 115, the clock tree 117, and the output buffer 120 together form a forward or internal clock path. In the context of this document, the term “forward clock path delay” refers to a clock delay occurring along the forward clock path from the input buffer 105 to the output buffer 120. Other systems can have additional components along their forward clock path. In such cases, part of the forward clock path delay can be associated with the additional components.
The input buffer 105 receives the external clock signal CLK. The input buffer 105 generates a reference clock signal clk with a delay from the external clock signal CLK. The input buffer 105 provides the delay line 115 and the phase detector 140 with the reference clock signal clk.
The delay line 115 receives the reference clock signal clk from the input buffer 105 and delays the signal. The delay line 115 includes a plurality of delay stages, for selection of a desired delay from the reference clock signal clk. The delay line 115 can include a daisy chain of logic gates.
The clock tree 117 receives the delayed signal from the delay line 115. The clock tree 117 is configured to distribute clocks for timing the internal circuits 170. The clock tree 117 also provides an output signal to the output buffer 120.
The output buffer 120 receives the output signal from the clock tree 117. The output buffer 120 provides an output signal CLK_DLL which is delayed from the clock tree output signal.
The replica model 125 receives a delayed clock signal from the delay line 115 and further delays the delayed signal. The replica model 125 is configured to emulate delays along the forward clock path of the system 100 except for a delay associated with the delay line 115. In the illustrated system 100, the replica model 125 can include a dummy output buffer, a dummy clock tree, a dummy input buffer, and additional gates (not shown) to form a replica of the forward clock path delay. The replica model 125 provides a replica model output signal to the phase detector 140.
The phase detector 140 compares the reference clock signal clk with the replica model output signal from the replica model 125. The phase detector 140 generates a comparison signal corresponding to a phase difference between the reference clock signal clk and the replica model output signal. The phase detector 140 provides the comparison signal to the shift register controller 142.
The shift register controller 142 receives the comparison signal, and controls the shift register 145 in response to the comparison signal. The shift register 145 is configured to select the delay amount of the delay line 115.